MARVELL 88E1512 DRIVER

I Have met the same problem, hope could get some ideas from you! I cant try it due to my situation, if you try it can you please give information about Build the device tree blob, and copy uImage and the. Product Selector Guide Access comprehensive product specifications for Marvell’s family of Transceivers products: I’ve tried your device tree example as well as different examples found:. Note that I am using two different sub-nets – the

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I will post when I get the new release and test it. Build the device tree blob, and copy uImage and the.

88EA0-NNP2I Marvell | Ciiva

I’ve verified that both PHYs respond when using the u-boot mdio commands, however, when running the Linux kernel code, it appears to ignore or not see the addresses in the device tree, and it also seems to not identify PHY1 correctly, attaching a “Generic PHY” driver to it.

It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured. Oddly, eth1 seems to receive packets even though the link is never detected. I recommend the device tree in the answer with any necessary modifications for your implementation.

The Alaska Gigabit PHYs build on the Marvell legacy of providing unique, best-in-class features that enable customers to expand their Ethernet applications. Did you try running ping with u-boot? I assume you use 88e15512 same interface voltage for both PHY chips.

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With design and support centers 88w1512 across the globe, Marvell provides comprehensive global engineering and technical support. I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond. Give Kudos to a post which you think is helpful and reply oriented.

It’s 88r1512 being released in the petalinux Haven’t worked on this in a couple of years. Link never comes up on eth1, although I can see received packets on the eth1 interface, as if the default PHY configuration is enough to receive packets in some form.

Access comprehensive product specifications for Marvell’s family of Transceivers products:. Reluctant to pursue it as we are not using Petalinux: Could you explain how to implement Xilinx provided patch at each these different steps? I’ve tried your device tree example as well as different examples found:. According to a Marveol FAE: Verified fix for this problem. Patch is applicable ONLY to the I will dig into the kernel code to see if there is a workaround.

We verified that before trying it in the kernel. If you want to achieve great things, then we want to talk with you.

Mxrvell this helps everyone with this problem There was a little communication confusion with Xilinx. It’s likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software.

We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Reluctant to pursue it as we are not using Petalinux:. However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth Driver Downloads Download the latest Marvell drivers for your specific device or application.

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Alaska Gigabit Ethernet PHYs Transceivers

However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: As Ethernet technology becomes more prevalent in everyday mainstream applications such as IP phones, gaming consoles, PDAs, printers, and traditional home or corporate network connections, the demand for energy efficiency and advanced process technologies increases.

Alaska Gigabit Ethernet PHYs Transceivers As Ethernet technology becomes more prevalent in everyday mainstream applications such as IP phones, gaming consoles, PDAs, printers, and traditional home or corporate network connections, the demand for energy efficiency and advanced process technologies increases.

The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1.