This chip is basically identical to the It also includes a fully programmable dot clock and supports all types of flat panels. Intel Corporation Chips and Technologies , Inc. XFree86 believes that the 8bpp framebuffer is overlayed on the 16bpp framebuffer. Also check the BIOS settings.

Uploader: Kigat
Date Added: 11 June 2007
File Size: 29.11 Mb
Operating Systems: Windows NT/2000/XP/2003/2003/7/8/10 MacOS 10/X
Downloads: 46617
Price: Free* [*Free Regsitration Required]

Information for Chips and Technologies Users

Options related to drivers can be present in the Screen, Device and Monitor sections and the Display subsections. Additionally, the ” Screen ” option must appear in the device section. Customer Impact of Change and Recommended Action: The ct chipset introduced a new dual channel architecture. This option forces the two display channels to be used, giving independent refresh rates.

The clocks in the x series of chips are internally divided by 2 for 16bpp and 3 for 24bpp, allowing one modeline to be used at all depths.

IBD MicroPCI VGA Card with C&T Contrloller

In this case enough memory needs to be left for the largest unscaled video window that will be displayed. This chip is specially manufactured for Toshiba, and so documentation is not widely available.

Secondly, the memory bandwidth of the video processor is shared between the two heads. Note that the ” -bpp ” option has been removed and replaced with a ” -depth ” and ” -fbbpp ” option because of the confusion between the depth and number of bits per pixel used to represent to framebuffer and the pixmaps in the screens memory.


It is possible to force the server to identify a particular chip with this option.

Information for Chips and Technologies Users

Note that it is overridden by the ” SWcursor ” option. It might affect some other SVR4 operating systems as well. But assuming your memory clock is programmed to these maximum values the various maximum dot clocks for the chips are.

Also for non PCI machines specifying this force the linear base address to be this value, reprogramming the video processor to suit. This problem has been reported under UnixWare 1. The formula to determine the maximum usable dotclock on the HiQV series of chips is.

However luckily there are many different clock register setting that can give the same or very similar clocks. This option can be used in conjunction with the option “UseModeline” to program all the panel timings using the modeline values.

Horizontal tecnnologies or jittering of the whole screen, continuously independent from drawing operations. If you are having driver-related problems that are not addressed by this document, or if you have found bugs in accelerated functions, you can try contacting the Xorg team the current driver maintainer can be technoogies at eich freedesktop.

In this way the expensive operation of reading back to contents of the screen is never performed and the performance is improved.


Gamma correction at all depths and DirectColor visuals for depths of 15 or greater with the HiQV series of chipsets. This information will be invaluable in debugging any problems.

Please read the section below about dual-head display. For this reason the default behaviour of the server is to use the panel timings already installed in the chip. By default it is assumed that there are 6 significant bits in the RGB representation of the colours in 4bpp and above. You are using a mode that your screen cannot handle. The servers solution to this problem is not to do doubling vertically.

Before using this check that the server reports an incorrect panel size. The driver supports the use of flat panel displays and CRTs. This option forces the LCD panel size to be overridden by the modeline display sizes.

Although the authors of this software have tried to prevent this, they disclaim all responsibility for any damage caused by the software. However, some machines cbips to have this feature incorrectly setup.

A basic architecture, the WinGine architecture which is a modification on this basic architecture and a completely new HiQV architecture.